IBIS Macromodel Task Group

Meeting date: 12 April 2011

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                              Radek Biernacki
Ansoft:                       Chris Herrick
                              Danil Kirsanov
Ansys:                        Samuel Mertens
                              Dan Dvorscak
                              Deepak Ramaswamy
                              Jianhua Gu
                            * Curtis Clark
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Mike LaBonte
                              Stephen Scearce
                              Ashwin Vasudevan
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                        Michael Mirmak
LSI Logic:                    Wenyi Jin
Mentor Graphics:            * John Angulo
                              Vladimir Dmitriev-Zdorov
                              Zhen Mu
                            * Arpad Muranyi
Micron Technology:          * Randy Wolff
NetLogic Microsystems:      * Ryan Couts
Nokia-Siemens Networks:     * Eckhard Lenski
Sigrity:                      Brad Brim
                              Kumar Keshavan
                            * Ken Willis
SiSoft:                     * Walter Katz
                              Mike Steinberger
                            * Todd Westerhoff
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group: * Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla

The meeting was lead by Arpad Muranyi

------------------------------------------------------------------------
Opens:

- None

- Ryan Couts introduced himself
  - He is at NetLogic designs TX/RX to inter-operate.

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Call for patent disclosure:

- None

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Review of ARs:

- Arpad add null output language
  - Done
  - Emailed, but no response

- Walter rewrite BIRD 123.1
  - Done

- All review draft

- Ambrish start a BIRD on task list row 25
  - In progress

- Bob write a BIRD on correcting Table 1-3 in the spec.  (Row 23).
  - In progress

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New Discussion:

Arpad called for discussion on the Crosstalk Clarification BIRD draft:
- Ken motioned to vote to submit the BIRD to the Open Forum
- Mike seconded the motion
- Roll call votes:
  Agilent:                    Y
  Ansys:                      Y
  Cadence Design Systems:     Y
  Cisco Systems:              Y
  Mentor Graphics:            Y
  Micron Technology:          Y
  Nokia-Siemens Networks:     Y
  Sigrity:                    Y
  SiSoft:                     Y
  Teraspeed Consulting Group: Y
- The motion passed

AR: Arpad submit Crosstalk Clarification BIRD to Open Forum

We discussed BIRD 123.2:
- Walter: This update is not yet submitted
  - Changes are expected today
  - There is much discussion on RX_Noise_Pad
  - Rx_External_Reference_Clock is a new parameter
    - If True EDA tool can generate clock_times vector
    - Default is False
- Arpad: Why is this In, not Info?
- Walter: It advertises the capability and also receives the flag
- Scott: We have no way to control clocks going into an RX
  - This is problematic for clock forwarded systems
  - With this option a model maker can provide a clock stream to RX
  - It can be used in a number of ways
  - The output clock_times can be 
- Ken: Does it make sense for traditional serdes?
- Scott: Maybe to model noise on the clock
  - The clock becomes another analyzable circuit
  - This can be another type of AMI simulation
- Walter: several clock jitter parameters can be used with RX GetWave
  that does not return clock_times
  - Sj with Freq means sinusoidal jitter
  - Sj w/o Freq applies at all frequencies
  - We can resolve any question on the reflector
- Fangyi: How does the model developer know the noise level?
- Walter: IC vendors will have to answer that
- Fangyi: Rj should be applied to clock_ticks?
- Walter: Yes
- Curtis: You can capture that and still get Dj

We discussed Table syntax BIRD proposals:
- Bob: We can document the existing usage of Table as it stands now
  - We can also use it for multi-row tables
  - AMI syntax does not require the first row to be a name
  - The type can be declared outside the table
  - AMI does not accept tables with no parentheses around the contents
  - Need to clarify labels

Arpad showed the Out-InOut BIRD draft:
- Arpad explained
- Ambrish: Can we have language to clarify that only reserved
  parameters can be used?
- Bob: We should say the EDA tool is not expected to modify files.
- Walter: We need to say the user can do anything with the model.
- Ambrish: But they will not be claimed to be IBIS compliant models.
- Walter: The user can tell the EDA tool to do anything.
- Arpad: Model users can't expect what the tool has not implemented.
- Scott: Specifications for how this works should be submitted
- Todd: This is about output Init not affecting simulation results?
- Scott: Correct
- Todd: There should be no problem
- Scott: The issue is undocumented behavior
  - New functionality should be brought to IBIS for approval
  - There are models with jitter parameters for which the meaning is not
    agreed
- Todd: We proposed changes publicly in 2010
- Arpad: We need feedback on the text of this BIRD proposal

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Next meeting: 19 Apr 2011 12:00pm PT

Next agenda:
1) Task list item discussions

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IBIS Interconnect SPICE Wish List:

1) Simulator directives
